This disclosure relates generally to the field of semiconductor device fabrication, and more particularly to fabrication of devices including fin field effect transistors (FinFETs) by sidewall image transfer (SIT).
The need to remain cost and performance effective in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of such semiconductor devices to be reduced. The push for ever increasing device densities in particularly strong in complementary metal-oxide-semiconductor (CMOS) devices such as field effect transistors (FETs). FETs are used in many types of integrated circuit (IC) design (i.e., microprocessors, memory, etc.). Unfortunately, increased devices density of FETs may result in degradation of device performance or reliability.
One type of FET that has been proposed to facilitate increased device performances is the FinFET. In a FinFET, a vertical fin structure is defined to form the body of the transistor. The fin structures may be formed on a substrate including a silicon on insulator (SOI) substrate. Gates stacks are then deposited on both sides and the top of the fin structures. The fin structures and/or gates may be defined by a technique referred to as sidewall image transfer (SIT). In one example of SIT, mandrels are formed on top of a thermal silicon oxide layer that is located above the SOI layer. A conformal SIT spacer is then formed over the mandrels, the spacer is etched back to expose the top surfaces of the mandrels, and the mandrels are removed, leaving the portion of the SIT spacer that was located on the mandrel sidewalls. During the SIT process, the thermal silicon oxide layer may be damaged. Any fluctuation in the thermal silicon oxide layer thickness at the end of the SIT process result in erosion of the fin structure during etching of the FinFET gate. Eroded fins might be difficult to merge together during subsequent epitaxial processing. Further, for a replacement gate integration scheme, a relatively thin layer of thermal silicon oxide (e.g., about 3 nanometers thick) on top of the SOI is required, which requires strict control of the thermal oxide thickness variation during the SIT etching. In the case SIT using a polysilicon mandrel, the thermal silicon oxide may be sloped after the polysilicon mandrel etch. In the case of SIT using an amorphous carbon mandrel, the thermal silicon oxide may be partially etched and result in thickness variations at the end of fin formation. Further, there is a risk that the thermal silicon oxide will be exposed during SIT spacer removal, so there is a risk that the thermal silicon oxide will be punched through during subsequent processing steps.